1. Field of the Invention
The invention relates to a method for quickly reading a data item from a dynamic memory cell. The invention also relates to a reading circuit and a dynamic memory circuit for carrying out the method.
2. Description of the Related Art
Dynamic semiconductor memories, such as dynamic random access memories (DRAMs), have memory cells with storage capacitors whose charge can be switchably applied to a bit line using a word line. To be able to detect the small charge in a storage capacitor, reading amplifier circuits are used which can detect the smallest charge differences between two adjacent bit lines. The reading circuits amplify the difference, brought about by the charge in the memory cell, between the electrical potentials on the respective bit line and a bit line which is adjacent thereto, and in so doing pull the bit line with the lower potential to a prescribed low potential and pull the bit line with the higher potential to a prescribed high potential. This amplification operation simultaneously serves to write back the charge information to the memory cell again.
The need for writing back means that the electrical potential on the entire bit line, which represents a high capacitive load, needs to be raised or lowered to the prescribed value. Only when the prescribed electrical potentials have appeared on the two bit lines is it possible to connect the information from the memory cell to the data bus. A particular drawback of this conventional concept is that the duration of the read operation is directly dependent on the time required for the change in potential on the bit line and hence on the duration of the write-back operation.
FIG. 1 shows an example of a reading circuit for a column of memory cells in a dynamic memory circuit based on the prior art.
Dynamic semiconductor memories, e.g., DRAMs, have a multiplicity of memory cells which are arranged in rows and columns in a matrix and which are usually addressed via word lines and bit lines. In this case, each memory cell is arranged on a word line and on a bit line and has a selection transistor and a storage capacitor, e.g., in the form of a trench capacitor. For the purpose of simplification, FIG. 1 shows just a single memory cell M which is connected to a bit line BL and a word line WL. The storage capacitor in the memory cell M can store a unit of information in the form of a prescribed charge. To read the content of the dynamic memory cell M, the selection transistor in this memory cell M is activated by means of the associated word line WL, and the memory cell M is therefore connected to the associated bit line BL. The charge which flows from the storage capacitor to the bit line BL in the process increases the electrical potential of the bit line BL. Since the bit line BL represents a high capacitive load for the memory cell M, the change in potential on the bit line BL turns out to be very small, however. To detect the electrical potential of the bit line BL, a reading amplifier SA is normally used which is in the form of a differential amplifier (sense amplifier). The reading amplifier SA compares the electrical potential of the bit line BL with the electrical potential of an adjacent bit line BL, the “complementary bit line”, and amplifies the potential difference which exists between the two lines BL, BL. In this case, that bit line which has the higher electrical potential is pulled to a prescribed high potential, and the other is pulled to a prescribed low potential.
Since the reading amplifier SA in a conventional reading circuit also has the task, besides that of assessing the information on the bit line BL, of writing back the information which has been read to the memory cell M again, the potential of the entire bit line BL must first be pulled to the prescribed value before the reading amplifier SA can be connected to the appropriate data lines and the information can be forwarded to the data bus DAT.
On account of the capacitive load which the entire bit line BL represents, the desired bit line potential does not appear until after a corresponding delay. For this reason, in the conventional concept, the information is forwarded to the data bus DAT only with the corresponding delay, with the duration of the entire read operation being directly dependent on the time required for the change in potential on the bit line BL and hence on the duration of the write-back operation.